Non-volatile memory devices are widely used in many consumer, commercial and other applications. While some non-volatile memory devices, such as flash memory, use accumulated charge to store data, some other memory devices, such as resistive random access memory (RRAM), phase change RAM (PRAM), and magnetic RAM (MRAM), use change in resistivity of a material therein to store data.
A resistive memory cell generally includes a first electrode, a second electrode, and a variable resistivity material connected therebetween. The resistive memory cell can be configured so that the resistivity of the material is controlled in response to a voltage that is applied between the first and second electrodes.
A PRAM device may include a phase changeable material layer which functions as a variable resistivity material. In response to sufficient heat, the phase changeable material layer may change phase so that its resistance changes and remains changed after its temperature returns to a pre-heating level. The phase changeable material layer may be formed from a chalcogenide material that includes germanium (Ge), antimony (Sb), and/or tellurium (Te). The phase of the material can be controlled in response to a level of current and/or duration of current that is applied to an electrode to heat the material a sufficient amount to change its phase. The resistance of the phase changeable material layer varies in response with its phase. For example, when the phase changeable material has a crystalline state, its resistance can be substantially less than when the phase changeable material layer has an amorphous state. Accordingly, the resistance of the phase changeable material in a PRAM device is controlled to store a logic value and is sensed to read the logic value.
FIGS. 1A-G are cross-sectional views illustrating a conventional method of manufacturing a phase changeable memory device. Referring to FIG. 1A, an electrical insulation layer 112 is formed on a substrate 100. The insulation layer 112 may be formed from, for example, silicon oxide and/or silicon nitride. A photo resist pattern is then formed on the insulation layer 112. The insulation layer 112 is patterned using the photo resist pattern as a mask to form an opening 115 that exposes a portion of the substrate 100. The opening 117 may expose, for example, an impurity region in the substrate 100 that serves as a conductive region for the memory device.
A semiconductor member having first conductivity type impurities is formed to partially fill the opening 115. The semiconductor member is formed by a selective epitaxial growth (SEG) process using the exposed portion of the substrate 100 as a seed layer.
A vertical cell diode 125 is formed in the semiconductor member within the opening 115 by doping an upper region 126 thereof with second conductivity type impurity ions while a lower region 128 of the semiconductor member has predominately first conductivity type impurity ions.
Referring to FIG. 1B, an ohmic layer 129 is formed within the opening 115 on the diode 125, such as by forming a metal silicide through the opening 115 on an upper surface of the diode 125.
Referring to FIG. 1C, an insulating spacer layer 130 is formed on upper surfaces of the insulation layer 112, sidewalls of the opening 115 above the ohmic layer 129, and on an upper surface of the ohmic layer 129. The spacer layer 130 is formed from silicon nitride at a temperature greater than 680° C. Referring to FIG. 1D, insulating spacers 135 are formed along sidewalls of the opening 115 by etching the spacer layer 130 to expose the upper surfaces of the insulation layer 112 and a portion of the ohmic layer.
Referring to FIG. 1E, a metal layer 142 is formed on the spacers 135 along sidewalls of the opening 115 and on the ohmic layer 129. A metal nitride layer 144 is formed on the metal layer 142 in the opening 115. The metal layer 142 and the metal nitride layer 144 serve as a first electrode layer 140.
Referring to FIG. 1F, an insulating filling layer is formed on the metal nitride layer 148 to fill a remaining portion of the opening 115. The filling layer may be formed at a temperature greater than 680° C. from silicon oxide or silicon nitride.
The filling layer and the first electrode layer 160 are etched to expose upper surfaces of the insulation layer 112. Etching the filling layer forms a filling member 155. Etching the first electrode layer 140 forms a cup-shaped first electrode 145 that includes a patterned metal layer 146 and patterned metal nitride layer 148.
Referring to FIG. 1G, a phase changeable material layer 170 is formed from a chalcogenide material on upper surfaces of the insulation layer 112, the filling member 155, and the first electrode 145. A conductive second electrode layer 180 is formed on the phase changeable material layer 170.